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MAX5890
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50
double-terminat-
ed, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA
≥ +25°C are guar-
anteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Settling Time
To 0.025% of the final value (Note 3)
11
ns
Glitch Impulse
Measured differentially
1
pV
s
IOUT = 2mA
30
Output Noise
NOUT
IOUT = 20mA
30
pA/
√Hz
TIMING CHARACTERISTICS
Input Data Rate
600
MWps
Data Latency
5.5
Clock
cycles
Data to Clock Setup Time
tSETUP
Referenced to rising edge of clock (Note 4)
-1.5
ns
Data to Clock Hold Time
tHOLD
Referenced to rising edge of clock (Note 4)
2.6
ns
Clock Frequency
fCLK
CLKP, CLKN
600
MHz
Minimum Clock Pulse-Width High
tCH
CLKP, CLKN
0.6
ns
Minimum Clock Pulse-Width Low
tCL
CLKP, CLKN
0.6
ns
Turn-On Time
tSHDN
External reference, PD falling edge to
output settle within 1%
350
s
CMOS LOGIC INPUT (PD)
Input Logic-High
VIH
0.7 x
DVDD3.3
V
Input Logic-Low
VIL
0.3 x
DVDD3.3
V
Input Current
IIN
-10
±1.8
+10
A
Input Capacitance
CIN
3pF
LVDS INPUTS
Differential Input High
VIHLVDS
(Notes 6, 7, 8)
+100
+1000
mV
Differential Input Low
VILLVDS
(Notes 6, 7, 8)
-1000
-100
mV
Internal Common-Mode Bias
VICMLVDS
1.125
1.375
V
Differential Input Resistance
RIDLVDS
110
Common-Mode Input Resistance
RICMLVDS
3.2
k
Input Capacitance
CINLVDS
3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
Clock Common-Mode Voltage
CLKP and CLKN are internally biased
AVCLK / 2
V
Minimum Differential Input
Voltage Swing
0.5
VP-P
Minimum Common-Mode Voltage
1V
Maximum Common-Mode
Voltage
1.9
V
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